SC Conference - Activity Details

Lakshminarayanan Renganarayana  (IBM T.J. Watson Research Center)

Uday Bondhugula  (IBM T.J. Watson Research Center)

Salem Derisavi  (IBM Toronto Research Laboratory)

Alexandre E. Eichenberger  (IBM T.J. Watson Research Center)

Kevin O'Brien  (IBM T.J. Watson Research Center)

Autotuning and Compilers

Tuesday,  02:00PM - 02:30PM

Room PB256

To achieve high performance on multi-cores, modern loop optimizers apply long sequences of transformations that produce complex loop structures. Downstream optimizations such as register tiling (unroll-and-jam plus scalar promotion) typically provide a significant performance improvement. Typical register tilers provide this performance improvement only when applied on simple loop structures. They often fail to operate on complex loop structures leaving a significant amount of performance on the table. We present a technique called compact multi-dimensional kernel extraction (COMDEX) which can make register tilers operate on arbitrarily complex loop structures and enable them to provide the performance benefits. COMDEX extracts compact unrollable kernels from complex loops. We show that by using COMDEX as a pre-processing to register tiling we can (i) enable register tiling on complex loop structures and (ii) realize a significant performance improvement on a variety of codes.

The full paper can be found in the ACM Digital Library and IEEE Computer Society