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Scalable Automatic Topology Aware Mapping for Large Supercomputers

Presenter:
Abhinav Bhatele  (University of Illinois at Urbana-Champaign)
Doctoral Research Showcase Session
Wednesday,  03:30PM - 03:45PM
Room PB252
Abstract:
This dissertation will demonstrate the effect of network contention on message latencies and propose and evaluate techniques to minimize communication traffic and hence, bandwidth congestion on the network. This would be achieved by topology-aware mapping of tasks in an application. By placing communication tasks on processors which are in physical proximity on the network, communication can be restricted to near neighbors. Our aim is to minimize hop-bytes, which is a weighted sum of the number of hops between the source and destination for all messages, the weights being the message sizes. This can minimize the communication time and hence, lead to significant speed-ups for parallel applications and also remove scaling bottlenecks in certain cases. The dissertation will involve developing a general automatic topology-aware mapping framework which takes the task graph and processor graph as input, and outputs near-optimal mapping solutions.
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